The disclosure relates generally to three dimensional silicon integration structures and more specifically to design and layout of through-silicon via (TSV) structures allowing for enhanced electromigration resistance.
In semiconductor technologies, a through-silicon via, also known as a through-substrate via, is a conductive feature formed in a semiconductor substrate (wafer or die). The TSV feature vertically passes through the semiconductor substrate, providing a stacked wafer/die packaging method and allowing electrical connection between circuits in separate wafers or chips.                There are a number of ways to create a TSV. Typically, a hole is etched into the semiconductor substrate, and sometimes through the interconnect structure as well. The hole may then be lined with various isolating layers and/or various metal layers. The hole is then filled with the conductive material, typically copper (Cu), which becomes the major part of a TSV. Some TSVs are in electrical contact with the semiconductor substrate, while others are electrically isolated. Any material within the etched hole may be considered part of the TSV, so the complete TSV may include the Cu, plus a liner, and perhaps insulating layers. Initially, the hole does not extend through the complete depth of the wafer. One side of the wafer is then subject to a thinning process (e.g. mechanical grinding, chemical-mechanical-polishing (CMP), or chemical or plasma etching) until the conductive metal of the TSV extends all the way through the semiconductor substrate. This side of the semiconductor substrate may be referred to as the grind side. The opposite side, where devices and the interconnect structure are located, may be referred to as the device side.        
A metallization layer is wiring embedded in a dielectric material. Multiple metallization layers are often put together and interconnected through conventional vias. These layers together may be called the interconnect structure, or the Back End of Line (BEOL) wiring levels. Though a conventional via shares some similarity of name with a through-silicon via, it is a substantially different structure bearing little relationship. A conventional via connects wires within the interconnect structure and may only pass through a single dielectric layer. Conventional vias are on the order of the sizes of the metal lines to which they connect, generally within a factor of three to four times the thickness in the worst case. A TSV, having to pass through an entire semiconductor substrate, may be as much as thirty times larger in diameter than the conventional via. This has the effect of necessitating that, when connecting circuits on one chip or wafer to another chip or wafer, extremely thin wires in a metallization layer must connect to the much larger TSV structure. The size of the TSV also allows for fidelity of shape. Because the diameter of minimum-sized conventional vias is at the limits of photolithographic resolution, shapes given to conventional vias end up essentially round. However, due to the greater shape fidelity of the TSV, surfaces, angles and edges in the design can be preserved in the shapes built into the wafer.
Electromigration can take place in any conductive material carrying a current, such as a TSV structure or a metallization layer. Electromigration is the transport of material caused by the gradual movement of ions in a conductor. This transport of material may eventually cause a gap, or a void, in the conductive material leading to higher resistance at other connection points, or an open circuit failure when all connection is lost. To reduce the occurrence of such voids, there are rules limiting the amount of current allowed in a conductive material. Such electromigration ground rules are well known within the art.